The edge stack moved on several fronts in the last week. NVIDIA launched the mainstream Jetson Thor T3000 and T2000 modules to bring Blackwell-class compute into cheaper, smaller robots; a developer-led effort proposed a standard BIOS-like firmware for RISC-V boards; Hygon posted RFC patches that extend the kernel’s new cache-aware scheduler across cache domains; and Seeed opened pre-orders for an open edge-AI camera built on the Rockchip RV1126B.
NVIDIA’s mainstream Jetson Thor T3000 and T2000 modules, the Harmonic Firmware Initiative proposing a BIOS-like environment for RISC-V, an RFC that extends cache-aware scheduling across scheduling domains, and Seeed’s RV1126B-based reCamera Pro.
This edition is mostly about the hardware and boot layers beneath edge Linux, with one kernel-internals item. The through-line is that edge AI is getting both more capable at the top and more standardised at the bottom, while the scheduler keeps being tuned for the multi-cache CPUs now common in servers and workstations.
In this edition
- NVIDIA launches mainstream Jetson Thor T3000 and T2000. Smaller, lower-cost Blackwell modules for robotics and edge AI, with emulation available now and hardware in Q1 2027 (CNX Software).
- A push to standardise RISC-V boot firmware. The Harmonic Firmware Initiative proposes a PC-style, BIOS-like environment that identifies hardware, runs POST-style checks, and hands off to U-Boot (The Register).
- Cache-aware scheduling extended beyond one cache domain. Hygon RFC patches let task grouping expand across scheduling domains, with large but scenario-specific benchmark gains (Phoronix).
- An open edge-AI camera on the Rockchip RV1126B. Seeed’s reCamera Pro pairs a 3 TOPS NPU with an 8MP sensor and runs vision, VLM, LLM, and speech models on-device (CNX Software).
Mainstream Jetson Thor: Blackwell compute at half the size
NVIDIA introduced two smaller, lower-cost additions to the Jetson Thor line, the T3000 and T2000, positioned below last year’s T4000 and T5000 modules (CNX Software, NVIDIA). The T3000 is rated at up to 865 FP4 TFLOPS and carries a 1536-core Blackwell GPU, an eight-core Arm Neoverse CPU, and 32 GB of LPDDR5X at 273 GB/s. The T2000 is rated at up to 400 TFLOPS with a 1024-core GPU and 16 GB of LPDDR5 at 137 GB/s. Both are roughly half the physical size of the T4000 and T5000.
The important number for planning is not the headline TFLOPS but the memory bandwidth. On these modules the GPU, the CPU, and the NPU share one LPDDR5X pool, so 273 GB/s on the T3000 and 137 GB/s on the T2000 is the ceiling that a vision pipeline, a camera stream, and a language model all draw from at once. A model that fits in memory can still stall if the bandwidth budget is already spent moving frames. When you size a workload for one of these parts, budget the bandwidth first and treat the compute rating as the easier constraint to satisfy.
On timing: the modules are scheduled for Q1 2027, but T3000 emulation is available this month through JetPack 7.2.1, with T2000 emulation to follow. That gap is useful. You can port and profile a BSP against the emulated target now and be close to production-ready when silicon arrives. Teams building robots or cameras on Jetson should start that port early rather than waiting for hardware, because the board bring-up and the Yocto or JetPack integration are usually the long pole, not the application.
A BIOS-like firmware for RISC-V boards
A developer-led effort called the Harmonic Firmware Initiative (HFI) proposes a standard, PC-style firmware environment for RISC-V machines (The Register, Phoronix). The idea is that when a board powers on, the firmware identifies the system, runs POST-style hardware checks, lists connected peripherals, offers a setup screen, and then hands over to U-Boot to load the operating system. The author is prototyping it on a SiFive HiFive Unmatched and has driven an old NVIDIA GK208 card in the PCIe slot to show a text boot display, without reusing any x86 BIOS code.
The problem this addresses is real. RISC-V board bring-up today varies from vendor to vendor, and the early boot flow, from the ROM through OpenSBI and U-Boot, is where a lot of embedded time is spent. A common, discoverable firmware layer would make boards behave more predictably and lower the cost of moving a product from one SoC to another.
Set expectations, though. This is one person’s proposal and early prototype, not a ratified specification and not something to design a product around yet. The value now is directional. RISC-V’s application-processor baseline has been settling through the RVA23 profile, and a firmware-level convention is the logical next layer. Watch whether RISC-V International or the major SoC vendors pick up the idea, because a proposal only matters here once silicon vendors ship it. For anyone teaching or learning embedded boot, it is a good lens on why firmware standardisation, not raw performance, is often what decides how painful a new board is to support.
Cache-aware scheduling stretched across cache domains
Cache-Aware Scheduling (CAS) merged into the mainline scheduler during the Linux 7.2 cycle, exposed through CONFIG_SCHED_CACHE, and it keeps tasks that share data inside the same last-level-cache domain to cut cache bouncing. Shortly after it landed, Hygon posted RFC patches that extend it beyond a single domain, letting task grouping expand or contract dynamically across scheduling domains (Phoronix). The reported gains are large in places: up to 360% higher MySQL throughput, about 49% on Hackbench, roughly 20% on Schbench, and around 30% on NVMe workloads.
Read the 360% figure carefully. It comes from a 64-thread MySQL delete workload with NUMA balancing enabled, a case where the existing scheduler’s cache logic fights NUMA balancing and scatters tasks, causing repeated cache-line invalidation. The patches target exactly that pathological interaction, so the number is real but not representative of a typical run. Most workloads will see far smaller effects.
You can check whether the merged CAS feature is present and inspect its runtime tunables:
raghu@techveda.org:~$ zcat /proc/config.gz | grep SCHED_CACHE
CONFIG_SCHED_CACHE=y
raghu@techveda.org:~$ ls /sys/kernel/debug/sched/The practical guidance is unchanged by the RFC. If you run database or memory-heavy services on multi-chiplet CPUs such as AMD EPYC or Intel Xeon 6, test the merged CAS option under your own load with the feature on and off before trusting any published number. The Hygon extension is still at the RFC stage and has not been reviewed or merged, so treat it as a signal of where the scheduler is heading, not as something to enable in production.
An open edge-AI camera on the RV1126B
Seeed opened pre-orders for the reCamera Pro, an open AI camera built on the Rockchip RV1126B, a quad-core Cortex-A53 SoC with a 3 TOPS NPU (CNX Software, Seeed Studio). It offers up to 4 GB RAM and 16 GB eMMC, an 8 MP sensor that reaches 4K at 30 fps, Gigabit Ethernet with PoE, and dual-band Wi-Fi. The NPU runs INT4, INT8, INT16, and FP16 models and takes TensorFlow, ONNX, PyTorch, and Caffe, and Seeed advertises not just detection models such as YOLO but also vision-language models, small language models, and speech-to-text and text-to-speech on the device. The 2 GB variant is listed at USD 299.90 with shipping from 29 July 2026.
The interesting shift is the claim that a 3 TOPS part can host VLM and LLM inference at all. It can, for small quantised models and short contexts, and that is precisely where the memory system decides what is possible. At INT4 the model weights shrink, but the sensor stream, the framebuffer, and the model still contend for the same modest DDR bandwidth, so throughput is governed by data movement rather than by NPU rating. A camera like this is a good teaching platform for that lesson, because the constraints are visible and the whole stack is open.
For product teams, the appeal is a single sealed unit that does capture and inference locally, which keeps data on the device and removes a network round trip. That maps directly to the on-device, private-inference direction that regulation and bandwidth costs are both pushing embedded products toward. This is the kind of full-stack edge Linux work, from the RV1126B BSP up to a quantised model, that we build our embedded and edge-AI training around.
References
- CNX Software — NVIDIA launches Jetson T2000 and T3000 modules
- NVIDIA — New Jetson Thor computers for mainstream robotics and edge AI
- Embedded.com — NVIDIA expands Thor modules for scalable robotics and edge AI
- The Register — RISC-V firmware project wants every board booting from the same hymn sheet
- Phoronix — HFI BIOS aims to provide a POST-like power-on screen and setup utility for RISC-V
- Phoronix — Cache-aware scheduling extended for even better performance: up to 360% in MySQL
- Phoronix — Cache-aware scheduling merged for Linux 7.2
- CNX Software — reCamera Pro open AI camera
- Seeed Studio — reCamera Pro 2GB
— Raghu Bharadwaj
