Edge AI in the Next 10 Years: The Long Horizon

An edge AI product you can build today has a well-understood shape: an NPU running quantized models on an embedded Linux platform, secure OTA updates, and — for deployed fleets — federated learning to improve models without centralising data. This article is about the forces that will reshape that architecture between now and 2035: the network, the exotic silicon, and the law. It closes with a concrete ten-year roadmap for where to point your skills.

For the present-day picture this builds on, we have covered the accelerator silicon in The Silicon Shift and the software stack in The Stack and the Fleet.

Three forces stand out: the network is becoming AI-native with 6G, a different class of silicon called neuromorphic is moving from laboratory to product, and a wave of privacy regulation is turning current good practice into legal obligation.

6G and the AI-native network

For most of mobile history, the network carried data and intelligence lived at the endpoints. 6G changes that arrangement. From the outset, 6G is being designed to be AI-native — AI is part of the network’s architecture and computing functions by design, not added afterward.

The standardization timeline: 2028–2030

This is neither speculation nor imminent, and getting the timeline right matters for planning. The path, as Ericsson lays it out, is well defined:

One milestone is already complete: 3GPP’s SA1 study on 6G service requirements (FS6G_REQ). The requirements are set and the technical design is underway.

The practical read for an engineer: 6G will not change your product before about 2030, but the architectural assumptions it introduces are being fixed now, and they are worth understanding early.

What AI-native means for edge devices

This is where 6G stops being only a telecom subject and becomes an edge AI subject. The standard under development defines AI capabilities directly into the network fabric:

• Network AI agents that handle user service intent and compose services dynamically to fulfil it.
• Third-party AI agent registration, discovery, and identification — your edge application’s AI could become a participant the network knows about and cooperates with.
• In-network AI model training and inference, with a full AI/ML lifecycle framework covering configuration, activation, verification, and testing — including fallback to conventional methods when the AI underperforms, a detail reliability engineers will appreciate.

The performance envelope is being sized for AI workloads explicitly: 3GPP’s Release 20 study material examined 6G uplink requirements in the range of 60 to 4,000 Mbps specifically for generative-AI applications.

The deeper shift is architectural. 6G merges connectivity, compute, and AI into a single continuum, which removes the old, hard boundary between “on-device” and “in-the-cloud”. The real design space of the next decade is a spectrum of compute placement, orchestrated dynamically between your device, the network edge, and the cloud. Systems that can move inference along that spectrum, rather than hard-coding where it runs, will stay useful longer than systems that cannot.

Neuromorphic computing: the long-range option

If 6G reshapes the network, neuromorphic computing could reshape the silicon itself. It is the most speculative topic in this article, and potentially the most consequential for battery-powered edge AI.

Event-driven efficiency

Conventional processors, including the NPUs that run mainstream edge inference today, follow the von Neumann model: compute and memory are separate, and moving data between them dominates the energy budget. Neuromorphic chips integrate compute and memory and process information with spiking neural networks that are event-driven — they consume power only when input signals change.

The efficiency numbers are large. Intel’s Hala Point, the largest neuromorphic system built to date with 1.15 billion neurons, performs on the order of 20 quadrillion operations per second at 2.6 kilowatts. Intel reports roughly 100x better energy efficiency than GPU-based systems on suitable workloads, and its research points to gains of up to 1,000x for compatible cases.

IBM’s NorthPole research chip demonstrated 22x lower latency and a 25x improvement in frames per second per watt against a comparable GPU on ResNet-50. For always-on edge applications, this class of efficiency is the difference between a device that lasts hours and one that lasts years.

Where neuromorphic wins, and where it does not

The field is crossing real milestones. In April 2025, researchers described what they believe is the first large language model adapted to run on an Intel Loihi 2 chip. The field also now has standardized measurement: the NeuroBench framework, published in Nature Communications in February 2025, provides a common methodology for comparing neuromorphic platforms.

The limits are equally real. Neuromorphic chips excel at sparse, event-driven tasks. They do not beat GPUs on dense workloads such as large-model training, and current inference chips carry genuine memory and accuracy limitations.

The realistic ten-year view: neuromorphic will not replace your NPU for general edge inference this decade. For a specific and growing class of ultra-low-power, always-on sensing workloads — the kind that run at the microcontroller end of the power spectrum — it deserves evaluation and occasional prototyping. Treat it as a strategic watch item, not a production plan.

Privacy, regulation, and compliance

A force that has quietly become one of the strongest drivers of edge AI adoption is regulation. GDPR, the EU AI Act, and India’s DPDPA all push processing toward the device, because data that never leaves the device is far easier to govern. On-device AI is increasingly a compliance-by-default strategy.

The EU AI Act timeline embedded engineers should track:

For high-risk systems, the obligations read like an embedded-systems engineering checklist: data governance, technical documentation and event logging, transparency and human oversight, robustness and cybersecurity, and traceability of model versions and training sets.

This is why secure boot, signed OTA, and audit-friendly update mechanisms matter beyond security: a hardened embedded Linux foundation built now is also a compliance foundation later. Engineers who treat logging, version traceability, and update integrity as first-class requirements today will not need to retrofit them in 2027–2028. (How to build that foundation on Yocto is the subject of The Stack and the Fleet.)

A ten-year field guide: what to do now

Bringing these forces together, these are the skills and stack elements worth investing in:

• Model quantization (INT8/INT4, post-training and quantization-aware) — the non-negotiable skill of edge inference.
• Yocto + NPU integration — clean, reproducible layers that make accelerator bring-up uneventful.
• Framework-neutral model pipelines — ONNX as the source of truth, vendor-compiled artifacts as build outputs.
• Federated learning — hands-on work with Flower, and an understanding of differential privacy for when the threat model demands it.
• Secure boot and signed OTA — safe field updates as a core product capability, not an afterthought.
• Compliance-aware engineering — logging, model version traceability, and audit trails built in from day one.

This is exactly the ground TECH VEDA’s Embedded Linux on EdgeAI platforms training covers. For working engineers on a compressed schedule, the Embedded Linux Fast-Track covers the same path along with the fundamentals of POSIX programming.

The phased view, 2026 to 2035:

Where this leaves us

The conclusion running through everything above is that edge AI is not a single technology — it is a convergence. Accelerator silicon, the embedded Linux software stack, federated learning, AI-native networking, neuromorphic hardware, and privacy regulation are all pushing in the same direction at once: intelligence moving to where the data is, on devices you build and maintain.

For embedded Linux engineers, that convergence is unusually good news. The skills that have always defined this discipline — building lean, secure, reproducible systems that extract the most from constrained hardware — are exactly the skills the next decade of AI demands.

You do not need to become a data scientist. You need to become the engineer who can take a model and make it run, safely and efficiently, on real hardware in the field, and keep it improving over time. The silicon is ready, the stack is buildable, the standards are forming, and the regulation is arriving. The best time to start building these skills is now.

Key takeaways

• 6G is being designed AI-native, with first commercial systems around 2030; the durable design principle is dynamic compute placement across device, network edge, and cloud rather than hard-coding where inference runs.
• Neuromorphic silicon delivers very large efficiency gains (Hala Point, NorthPole) but only for sparse, event-driven workloads — prototype it for always-on sensing, do not plan production on it this decade.
• The EU AI Act timeline (2025–2028) turns logging, model version traceability, and signed updates into legal requirements; a hardened security stack is also a compliance stack.
• The near-term work is unchanged by any of this: quantization, Yocto + NPU integration, ONNX pipelines, federated learning, and secure OTA.
• A phased roadmap keeps effort focused: production inference now, fleets and 6G pilots mid-decade, frontier evaluation from 2031.

Frequently asked questions

When will 6G actually matter for edge AI products?
Around 2030 for commercial systems, with pre-commercial trials from 2028. It will not change products shipping before then, but its architectural assumption — inference placed dynamically between device, network edge, and cloud — is worth designing toward now.

Will neuromorphic chips replace NPUs?
Not this decade. Neuromorphic chips win on sparse, event-driven workloads such as always-on sensing, where efficiency gains reach 100x or more, but they do not beat GPUs or NPUs on dense workloads and current chips have memory and accuracy limitations.

What does the EU AI Act require from embedded engineers?
For high-risk systems: data governance, technical documentation, event logging, human oversight, robustness and cybersecurity, and traceability of model versions and training sets. Full high-risk obligations apply from August 2027, with an extended transition to August 2028 for AI embedded in regulated products.

What should I learn first if I am starting today?
Model quantization and Yocto-based NPU integration, on a hardened Yocto LTS baseline with secure boot and signed OTA. These near-term skills carry unchanged through the whole ten-year roadmap.

Further reading

• Ericsson — 6G: connectivity and beyond for the 2030s and 6G standardization timeline and technology principles
• Ericsson — 6G standardization: the technology realization step begins
• 3GPP Release 20 — An update on 3GPP 6G technology studies (video)
• Intel — Hala Point, the world’s largest neuromorphic system
• IBM Research — The NorthPole AI chip
• Nature Communications — The NeuroBench framework for benchmarking neuromorphic computing and PNAS — Can neuromorphic computing help reduce AI’s high energy cost?
• European Commission — Regulatory framework for AI (AI Act) and Etteplan — Secure edge AI under the EU AI Act