BSP Tracker / BSP Status / AMD (Xilinx)
AMD Zynq UltraScale+ MPSoC
Upstream since v4.1 and AMD upstreams aggressively; the usual 'the BSP is ancient' argument simply does not apply here. You can ship a mainline PS-side Linux. What you do NOT escape by going mainline is Vivado/Vitis: the PL bitstream can only come from AMD's tools.
Mainline instead of the vendor BSP
Can you ship mainline instead, and what exactly do you lose if you do?
Mainline is shippable
| Block | IP | Upstream | Detail |
|---|---|---|---|
| FPGA manager | PL / partial reconfiguration | upstream | drivers/fpga has zynqmp-fpga, xilinx-pr-decoupler and friends. Bitstream LOADING works on mainline; producing the bitstream still needs Vivado. |
| VPU encode | Allegro DVT VCU | upstream | drivers/media/platform/allegro-dvt; Kconfig names the ZynqMP EV family explicitly. |
| VPU decode | VCU | missing | allegro-dvt is an ENCODER driver. No mainline ZynqMP VCU decoder found. |
| GPU | Mali-400 MP2 | upstream | gpu@fd4b0000 in mainline zynqmp.dtsi declares arm,mali-400; driven by the in-tree lima DRM driver. |
Vendor BSP
Repository. https://github.com/Xilinx/linux-xlnx
Newest branch that actually exists. xlnx_rebase_v6.18_LTS, tracking Linux 6.18. Last commit 2026-07-01.
Cadence. A clean annual LTS rebase: 5.15 -> 6.1 -> 6.6 -> 6.12 -> 6.18, each with a matching update branch. The freshest vendor tree of any SoC here.
Silicon longevity
Committed until 2045. AMD states UltraScale+ device lifecycles are extended through 2045, and a minimum 15-year lifecycle for new families. This is a blog announcement, not a per-OPN table — confirm for a specific XCZU part.
Yocto
Layer. meta-xilinx. A branch for the current LTS exists: wrynose.
A real wrynose branch now exists (HEAD 2026-07-22). meta-xilinx-core/conf/layer.conf declares LAYERSERIES_COMPAT_xilinx = 'wrynose' and pins XILINX_RELEASE_VERSION v2026.1 on linux-xlnx 6.18; it ships zynqmp-generic.conf plus the cg/dr/eg/ev machine variants, so the LTS gap is closed. The wrynose-next staging branch still exists alongside it.
Hardware you can buy
Evaluate on. ZCU102, ZCU104, Kria KV260 Vision AI Starter Kit
Production modules.
- Kria K26 SOM (XCK26) — AMD
- UltraZed-EG SoM — Avnet
- TE0808 UltraSOM+ (ZU9EG) — Trenz Electronic
What to do about it
AMD Zynq UltraScale+ MPSoC: upstream fixes stop December 2028. That leaves 28 months. After that date the kernel this BSP is based on receives no further security fixes from upstream, and maintaining it becomes your team’s responsibility.
There are three options:
- Backport the fixes yourself. Your team maintains a kernel that nobody else maintains: tracking each CVE, applying the patch to a tree that has diverged from upstream, and testing the result, for as long as the product ships.
- Move to the vendor’s newer BSP. This gives you a few more years of upstream fixes, and it costs a second bring-up: a new kernel, your patches forward-ported, drivers re-validated, and the product re-tested.
- Move to mainline. Mainline supports this SoC, so the migration is substantial work but not research. It is the only option that does not have to be repeated when the next vendor kernel reaches end of life.
All three are engineering work, and all three are work we do: reading vendor kernel trees, checking what mainline actually supports, and moving products from one to the other. This page is built from the same work.
Get the updates
An email when a kernel series reaches end of life, a board row changes, or a layer picks up a release branch. Nothing else.
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